Last term I took a course that involved a lot of FPGA programming. We used Altera’s DE2 development board as well as their example labs (Digital Logic and the first few Computer Organization labs). While the labs were quite enjoyable and very educational, it was a LOT of work compared to labs in other courses. This was also my first experience with Verilog (or any HDL for that matter) which didn’t help. Getting help with these labs was a bit tough as my classmates were all in the same boat, plus the professor and TA hadn’t done the labs yet. I have decided to post my solutions to these labs in case someone else down the line needs help with them too. I have included a README file with the code with a little more information and emails (or comments on this post) are welcome.

As an aside, I am currently hosting my code at github.com, but am debating switching to Gitorious (they seem to be more open source friendly) or possibly self hosting (Gitorious can be self hosted, or I might try cgit or Redmine). Does anyone have any thoughts on these? Perhaps other suggestions? I would love to self host, but the redundant offsite backups these services provide is always nice. Perhaps I will have to invest in a secondary, offsite server so I can do my own.